Overview
This is a 7-bit, current-mode SAR ADC in sky130A at VDD = 1.8 V, modeled after the converter by Hammerschmied & Huang. The architecture is interesting because it utilizes the matching of MOSFET I-V curves to construct an M2M ladder. This, combined with the fact that it doesn't require trimming to hit a moderate resolution target, made it an attractive option to implement.
The converter achieved 0.079LSB of INL, -57.6 dBc THD, and a 1 MS/s sampling rate. This corresponds with an ENOB of 6.94. The power consumption of the core analog design is roughly 5.4pJ/conversion step.
Input Stage
The V-to-I converter turns the differential input into two complementary currents I1, I2 with I1 + I2 = I_FS.
The cascodes are regulated by a folded cascode op-amp. A DC gain of 50dB guarantees that the source node tracks the input within 1mV. Compensation capacitors on the output ensure that the phase margin is over 60 degrees.
M2M Ladder
The M2M ladder splits I_FS into I_D1 = k·I_LSB and I_D2 = I_FS − I_D1 for the trial code k. I designed the ladder so that it has an R_on of 30k and an I_FS of 20uA, which corresponds to a roughly 0.6V swing. In general, a higher output resistance leads to less current error, but eats headroom. This was a reasonable compromise considering it is well within my target of 0.5 LSB of error on DNL and INL.
Summing Stage
The core idea of this converter is that the process of collecting the current from the ladder is separated from the conversion of the current to a voltage. This allows the output of the ladder to be very low impedance, reducing offset, while still producing a voltage large enough for the comparator to differentiate.
Regulated cascodes hold the ladder outputs at V_ref1 and the input-current nodes at V_ref2, so neither current divides into a finite output resistance. Each delta-I node is where a PMOS cascode (input side) meets an NMOS cascode (ladder side). The current it carries is the difference.
The regulated cascode setup is similar to the input stage. Each op-amp was designed for the common mode ranges it handles as well as to have enough gain to keep the source node error at less than 2mV. I again used a folded cascode amp for the PMOS cascode because of headroom constraints.
Output Stage
At this point, since the comparator provides a binary output, nonlinearity is intentionally introduced to make LSB current differences easier to detect. A clamp cell on each delta-I node turns the error current into a voltage around V_MID and controls the swing.
The comparator then decides whether the applied code is larger or smaller than the input. It was designed to be able to correctly resolve a 5mV difference in under 15ns with a small kickback and input capacitive load. The paper used this two-phase strongarm latch style design, which I decided to keep because it helps minimize offset.
Next Steps
All reported results are at TT, 27C. Corner analysis is necessary to ensure that devices remain in saturation and that the design meets its performance requirements.
The comparator and V-to-I converter are both susceptible to offset. This can create wrong decisions and introduce extra nonlinearity in the system. These blocks should be simulated with device mismatch models.
All biasing comes from ideal sources, so a bias generation scheme would need to be implemented for a tapeout.
The current SAR controller is currently being simulated as a fully digital block. A hardened macro would be necessary for a tapeout.
Prior Work
This project began its life as the final for my mixed-signal VLSI course, which you can read the report for below. There were a few glaring issues with the design that led to subpar linearity.
The first is that the comparator did not properly reset, as the switch that shorts the latch nodes wasn't strong enough to overcome the positive feedback. The reset switch should exhibit:
gm,on ≥ 3gm,latch
This led to a "memory" of the last conversion persisting for small LSB changes, which is why the transfer curve looks stuck at a few levels.
The second is that the regulated cascode op-amps simply did not provide enough gain to hold the ladder output nodes constant. This introduced an offset voltage at the output of the ladder which leads to a current error and thus poor linearity.
I came back to this almost a year later because I plan on doing more data converter design, and it didn't feel right to leave it in a broken state. The new design is roughly a 99.2% improvement in terms of linearity, which is more than I expected. Regardless, a lot of work went into this original project. A lot of the layout and LVS efforts were valuable learning experiences and it was fun to revisit with more knowledge and do a better job.
